JOSTALY TECHNOLOGIES John SETH Thielemann sthielemann@jostaly.com +1-223-231-3511 (1755536322 UNIX 229) Mon Aug 18 16:58:42 2025 - (1756295826 UNIX 238) Wed Aug 27 11:57:06 2025 0 Company News) * Down for a week from surgery. * Revist various aged checkboxes: * Finish up first round of ARM MMU flat mapping support and UT. * Integrate with existing multi-processing infrastructure. * Proper exclusive access on ARM (outside of local cpu), revisit various assembly. * Build test harnesses for various drivers that were lacking. * Some performance boosting. * Significant size reduction. * Revise build for better automation, testing, various flags, build summary, statistics. * Use hardware for redundancy/independent checks for various computations and rework. * Begin language processing and starting on various related utilities. Completed 30/50 checkboxes, 183 files changed, 10792 insertions(+), 2963 deletions(-) Attachment (linux platform elf MMU test stub) f7178814132862e2944de902121ec3155bea842bcd0091ffbeb915f2633ae514 @offset:0x000004D0 size: 63864 Attachment (ARM kernel elf MMU test stub ) 06bcbf4cf91070a242a0437bd46c4697fedd52267d10ad2a97834eaf669d04de @offset:0x0000FE48 size: 70800 ELF>@@x@8@@@@@@@AA@@00Std@@00Qtd GNU H1d @9t wHHcH1DÐ ff fffHfDAVAUATUSH0H;wHD$HHtyHILT$HIIJ I@HGHvF1E1HIIIMAL\$IIDd$D8<L;\$1t ;HI9sHMHHII HD$MI!HHHtLgIvIMLLMHl$(IՈ\$ @@8L;l$(@tIM9gH1LHHueHu@DHHttHƒt.t(Hv tHvHt HuHHAH0D[]A\A]A^!AWAVAUATUSH(L7H4$MHHH?~11LIHHLIH$M$8uLL;$uBu>LHHHH$HL$8uL;$u t kA>U'uH$L#MtM9r1҉MIHLL@H[@$MH$H\$0ILLL㈄$H$A@uA8uL9yEpI9gH9^M)L?HD$JMII]H\$ 4?I9&HnHI;^0 AIF HHD$HIMHtUIV(HvK11HIHLH$HHƈ$AA8H;$Et HH9sL HL$HJHHHH HD$HL!I9MHLL$3HEL;h0*DI HD$PHHH HuH@(Hg1HIHLAHH$HD$@D8H;$@HI9J H|$PHHHHHD$PH!H9tHD$h@H$L(IEHD$`I9RHLL$tO1H@HH@H@H$@$HD$@@8 H;$tHD$f)D$`Ld$`LL$LuLeLt$`LL$I>U'LLL$9M;nIFH<$HD$(H;GpLH|$01LL$@?HHH|$(HH9H)It=LL$0E1HHD$pHHD$/KHT$xLL$0HtSLL$8LILH\$0IHH|$mHD$p<(HH9uH\$0LL$8LMLLL$@I~LL$tH|$(t1IVHI;FrLLL$LL$H|$HHGHv0H|$LI>fH @H9uH|$H9|$HD$H|$H)HPHvHI>HHH|$tiH|$Ht$HGA>H9sQHGAD>H9sBHGAD>H9s3HGAD>H9s$HGAD>H9sHGAD>H9sAD>LuM[MLT$ Ll$XIHEH?=11LHHHLH$$8H;$M;V0HD$XIV HLLT$IF(H2E11HILHLH$HHֈ$@@8H;${@HH9LLHHHH HD$XLH!IIV HIv(HIIMM@IL$I@$AA8L;$EFHH99L1H HHHu@HHttHƒt.t(Hv tHvHt HuIV HLT$H@ @HHttHƒt.t(Hv tHvHt HuLuMH$f)H([]A\A]A^A_1^ ff.AWHAVAUATUSHHD$HD$H=o11HAHLHHL$8T$08H;D$8t f)D$Ht3H|$EH $H $L$f11L)$)$)$ fH$)$)$ Hl$p1f1H)D$`Ld$`H\$@afod$pLf)D$pL$)$\fH)D$@^L^YH$ <Hl$HDŽ$HDŽ$HDH\$H @LL$fo$fo$HpHpL@fo$fo@)@H$Hxfo$foPHǃxfo`HH$H)P)`H$H$)$)$)$[LL$[L~[Lv[HCH#@LLd$`H5HDŽ$H$L$HDŽ$ LL LL8 H$H5Lu LLj H5!LHS LHH HHfHnfHnHflH)D$ sHH1HHHD$ HD$(L$`Ht$h85H9,HD$ HH$;7HAIAf.DG€@E‰G1fG€@E‰G1fGƒ@E‰G1f f.fHHw@u HGPSHN0HHtHH[fHHv8Ht$HH@HtHpHtHHLHH[fo(H[SU0HHHH11HIHLHHt$8uH9T$uHf1x f.fSH foHFHfH~)$H4H9HHt?Ht7fs1fH~HHH$HD$L$Ht$8uaH9u\tf)$HHtH|$HH H[HsHt,HCHt#HstHHDH|$HH H[fD f.f f.f f.fHHH7HWuNIIrFHHt2H@t)IILL@HHL$@8uI9utf)Hf.HHtHHWHt?H11HIHLHHt$8uH9T$uHf.1HHH7HWuOIIrGHH?v2H@t)IILL@HHL$@8uI9utf)H)fHHtHHWH?v>H11HIHLHHt$8uH9T$uHf1H8HVHHtpHfHnHfHnfl)HHHt11HH@HHPHt$@8H9tf)H8ffoFH~HvfH~L7I9HHAtwHfH~IHLAHT$HH@D8uBH;T$u;@u?I)Au*HII@HHPLD$(@8u L9O@f); f.fHHtHHWHv>H11HIHLHHt$8uH9T$uHf1 f.fSH L_L9JI)HLHI9IIFHLEI?MtMHwHvC11LIHLIHT$LMʈ$8L;T$t DcHHI9sKHt2H@H)HHHH9IL9LHHH H@IL9sfHtHv11IHLIHT$LMʈD$8u;L;T$u4XI9OKHtHHHI9LGH L[f.DH@wAH?HH@v1AWIAVIAUATUSH(H@tHHHI!HHt]HMLIHOHv>11HIHLHH\$HՈ$8]H;l$Rt HHH9sJELHL Ht1E1IIIMMAILl$IDd$AE8L;t$EuHH9yLHH*HHHu@fHHttHƒt.t(Hv tHvHt HuH $HHfDHHLu LH! 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X P@S PJN 4p +  rPi  j l oOPpoOoOoOoOoOoOoO WoOW p&倐 `<P @@ߍ@@ߍ@@@P D~P H P ` R< @DLPTX`dHhxl|\  <P @@DP D?P H P  RoO2oO<(`P) RS ԃV< PF!D8""     P: @ P1 `pV<0F 0 P%!D B9""     P @  P `pVoO4 P2oO8 P- @&;0,(9&<  R R Q8@P :DP `pVoO, P2oO0 P` p ` 1oO`oOoOPoOoO0oOpoO AV @@@@ 0SL ZM YU RXLRWS 0 RK PJgPIP JOP JP JPIV@P J@}@y @u @q @m@~ @h}@dy@`u C@Yn@Uj@Rg@Nc I O-lM?@p@0 ` P$oP jPu "! 0$ sn*SR Ёq 0#03S^R\SX Y  0s0`#`3VKZHV00P@ Y>  08+P5 P X 0 0s0S' P%0 0s0S[0 `v`V[Z :P 0 lЍO@-0 4H0P#PoO0 1C6CCPoOPoO  PoOp@-P@P%0 4H+Pe1oO QoO  QoOQoO      oO p@p0P5PoOPoOPoOP:P SS S S pPoO0 i1C6CCPoOPoO  PoON interruptsinterrupt-parent#interrupt-cellsinterrupt-controller#clock-cells#size-cells#address-cellsphandleregcompatible 7S83(3V2P-CA9" arm,vexpress,v2p-ca9arm,vexpress+<Kbus@4000000 simple-bus<KPW@DHL^ o?            !!""##$$%%&&''(())**motherboardV2M-P1 arm,vexpress,v2m-p1simple-bus<K^Wflash@0,00000000 arm,vexpress-flashcfi-flashpartitions arm,arm-firmware-suitepsram@2,00000000 arm,vexpress-psrammtd-ram ethernet@3,02000000 smsc,lan9118smsc,lan9115 miiusb@3,03000000 nxp,usb-isp1761 iofpga@7,00000000 simple-bus<KWsysreg@0 arm,vexpress-sysreg<K Wgpio@8 arm,vexpress-sysreg,sys_led(gpio@48 arm,vexpress-sysreg,sys_mciH(gpio@4c arm,vexpress-sysreg,sys_flashL(sysctl@1000 arm,sp810arm,primecell 4;refclktimclkapb_pclkG0Ttimerclken0timerclken1timerclken2timerclken3 gwi2c@2000 arm,versatile-i2c <Kpcie-switch@60 idt,89hpes32h8`aaci@4000 arm,pl041arm,primecell@ 4 ;apb_pclkmmci@5000 arm,pl180arm,primecellP   4;mclkapb_pclkkmi@6000 arm,pl050arm,primecell` 4;KMIREFCLKapb_pclkkmi@7000 arm,pl050arm,primecellp 4;KMIREFCLKapb_pclkuart@9000 arm,pl011arm,primecell4 ;uartclkapb_pclkuart@a000 arm,pl011arm,primecell4 ;uartclkapb_pclkuart@b000 arm,pl011arm,primecell4 ;uartclkapb_pclkuart@c000 arm,pl011arm,primecell4 ;uartclkapb_pclkwdt@f000 arm,sp805arm,primecell4;wdog_clkapb_pclktimer@11000 arm,sp804arm,primecell4;timclken1timclken2apb_pclktimer@12000 arm,sp804arm,primecell 4;timclken1timclken2apb_pclki2c@16000 arm,versatile-i2c`<Kdvi-transmitter@39 sil,sii9022-tpisil,sii90229ports<Kport@0endpoint port@1endpoint dvi-transmitter@60 sil,sii9022-cpisil,sii9022`rtc@17000 arm,pl031arm,primecellp4 ;apb_pclkcompact-flash@1a000 arm,vexpress-cfata-genericclcd@1f000 arm,pl111arm,primecell combined4 ;clcdclkapb_pclk7 portendpoint  fixed-regulator-0 regulator-fixed!3V302ZH2Z`clk24mhz fixed-clockGtn6 Tv2m:clk24mhzrefclk1mhz fixed-clockGtB@Tv2m:refclk1mhzrefclk32khz fixed-clockGtTv2m:refclk32khzleds gpio-ledsuser1v2m:green:user1  heartbeatuser2v2m:green:user2 mmc0user3v2m:green:user3 cpu0user4v2m:green:user4 cpu1user5v2m:green:user5 cpu2user6v2m:green:user6 cpu3user7v2m:green:user7 cpu4user8v2m:green:user8 cpu5mcc arm,vexpress,config-busoscclk0 arm,vexpress-osc}x@G Tv2m:oscclk0oscclk1 arm,vexpress-oscjep@G Tv2m:oscclk1 oscclk2 arm,vexpress-oscn6n6G Tv2m:oscclk2 volt-vio arm,vexpress-volt!VIO`VIOtemp-mcc arm,vexpress-tempMCCreset arm,vexpress-resetmuxfpga arm,vexpress-muxfpgashutdown arm,vexpress-shutdownreboot arm,vexpress-reboot dvimode arm,vexpress-dvimode chosenaliases5/bus@4000000/motherboard/iofpga@7,00000000/uart@90005/bus@4000000/motherboard/iofpga@7,00000000/uart@a0005/bus@4000000/motherboard/iofpga@7,00000000/uart@b0005/bus@4000000/motherboard/iofpga@7,00000000/uart@c0005/bus@4000000/motherboard/iofpga@7,00000000/i2c@160004/bus@4000000/motherboard/iofpga@7,00000000/i2c@2000cpus<Kcpu@0 cpu arm,cortex-a9cpu@1 cpu arm,cortex-a9cpu@2 cpu arm,cortex-a9cpu@3 cpu arm,cortex-a9memory@60000000 memory`@reserved-memory<KWvram@4c000000 shared-dma-poolL& clcd@10020000 arm,pl111arm,primecell combined ,4;clcdclkapb_pclkportendpoint  memory-controller@100e0000 arm,pl341arm,primecell4 ;apb_pclkmemory-controller@100e1000 arm,pl354arm,primecell-.4 ;apb_pclktimer@100e4000 arm,sp804arm,primecell@01 4;timer0clktimer1clkapb_pclk -disabledwatchdog@100e5000 arm,sp805arm,primecellP 34;wdog_clkapb_pclkscu@1e000000 arm,cortex-a9-scuXtimer@1e000600 arm,cortex-a9-twd-timer   watchdog@1e000620 arm,cortex-a9-twd-wdt  interrupt-controller@1e001000 arm,cortex-a9-gic^<4cache-controller@1e00a000 arm,pl310-cache +IW c tpmu arm,cortex-a9-pmu0<=>?dcc arm,vexpress,config-busextsaxiclk arm,vexpress-oscÀG Textsaxiclkclcdclk arm,vexpress-oscĴGTclcdclktcrefclk arm,vexpress-osc@G Ttcrefclkvolt-vd10 arm,vexpress-volt!VD10`VD10volt-vd10-s2 arm,vexpress-volt!VD10_S2`VD10_S2volt-vd10-s3 arm,vexpress-volt!VD10_S3`VD10_S3volt-vcc1v8 arm,vexpress-volt!VCC1V8`VCC1V8volt-ddr2vtt arm,vexpress-volt!DDR2VTT`DDR2VTTvolt-vcc3v3 arm,vexpress-volt!VCC3V3`VCC3V3amp-vd10-s2 arm,vexpress-ampVD10_S2amp-vd10-s3 arm,vexpress-ampVD10_S3power-vd10-s2 arm,vexpress-power  PVD10_S2power-vd10-s3 arm,vexpress-power  PVD10_S3hsb@e0000000 simple-bus<K W ^o`$%&' modelarm,hbiarm,vexpress,sitecompatibleinterrupt-parent#address-cells#size-cellsranges#interrupt-cellsinterrupt-map-maskinterrupt-mapregbank-widthinterruptsphy-modereg-io-widthsmsc,irq-active-highsmsc,irq-push-pullvdd33a-supplyvddvario-supplyport1-otgphandlegpio-controller#gpio-cellsclocksclock-names#clock-cellsclock-output-namesassigned-clocksassigned-clock-parentscd-gpioswp-gpiosmax-frequencyvmmc-supplyremote-endpointreg-shiftinterrupt-namesmax-memory-bandwidthmemory-regionarm,pl11x,tft-r0g0b0-padsregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onclock-frequencylabellinux,default-triggerarm,vexpress,config-bridgearm,vexpress-sysreg,funcfreq-rangeserial0serial1serial2serial3i2c0i2c1device_typenext-level-cacheno-mapstatusinterrupt-controllercache-unifiedcache-levelarm,data-latencyarm,tag-latencyinterrupt-affinityInfo:Result: Heap ^ : initial : available: finished : TFHeap LEAKunreleased index: Initialization Cpu (0)\ `$````D` ````GCC: (Buildroot 2021.11-11272-ge2962af) 13.2.0A4aeabi*7-A A  "*D.shstrtab.text.rodata.plt.bss.comment.ARM.attributes `xx`x9|`|4``@#0/,p5<